The present invention generally relates to integrated circuits, and, more particularly, to scan flip-flop circuits.
Integrated circuits (ICs) such as a system on a chip (SoC) integrate various digital as well as analog components on a single chip. Designs of SoCs may have manufacturing defects, such as short circuits, open circuits, material defects, and damaged vias. Such manufacturing defects can cause the SoC to malfunction. Therefore, it is essential to test the SoCs for manufacturing defects.
Design for testability (also referred to as design for test or DFT) are design techniques that add testability features to the ICs. DFT enables Automatic Test Equipments (ATEs) to execute various fault test methods using test patterns generated by Automatic Test Pattern Generators (ATPGs). Each test pattern includes a set of bits. The ATPG sets the logic state of the each bit based on the type of fault to be tested in the IC.
Conventionally, fault test methods are categorized into two types—functional testing and structural testing. Functional testing uses functional or operational test patterns generated by verification engineers to test the functional characteristics of an IC. However, due to technological advancements that have vastly increased the number of components on a chip, the complexity and time required for generating functional test patterns has increased, thereby increasing the time and cost of testing. Structural testing (also referred to as scan testing) models the manufacturing defects as logic faults that are detected using simple memory elements such as flip-flops (also referred to as scan flip-flops) connected to each other in a chain (i.e., a scan chain), within the IC.
Scan testing has two modes, scan-shift and scan-capture. The scan-shift mode includes shift-in and shift-out modes. When scan testing is activated, the IC is set in the scan-shift mode. In the scan-shift mode, an ATPG generates a test pattern (also referred to as a test vector V1) and provides the test pattern to the ATE. The ATE shifts the test pattern, which is just a set of bits, into the scan flip-flops. Each bit of the test pattern is shifted in to the scan flip-flops based on consecutive clock pulses of a clock signal. The scan flip-flops operate as shift registers and shift the bits through the chain. At the end of the scan-shift mode, each scan flip-flop of the scan chain holds a corresponding bit of the test pattern.
When the test patterns is loaded into the IC, the IC undergoes logic state transitions based on the test patterns and a scan enable signal.
During the scan-capture mode, the scan flip-flops capture the logic state transitions of internal combinational logic of the IC based on a scan clock signal. Thus, each scan flip-flop stores a bit corresponding to the output of multiple logic modules of the IC.
After the completion of scan-capture mode, the IC is set in the scan-shift mode so that the stored bits can be shifted out of the IC (referred to as a test vector V2) and compared against an expected pattern. The ATE differentiates between functional and faulty ICs by comparing the output test pattern with the expected output test pattern.
FIG. 1A is a schematic block diagram of a conventional scan flip-flop circuit 100. The scan flip-flop circuit 100 includes a multiplexer 102, a master latch 104, a NOT gate 106 and a slave latch 108. The scan flip-flop circuit 100 has a clock input terminal (CLK) for receiving a clock signal and a scan enable input terminal (SE) for receiving a scan enable signal. The multiplexer 102 has a first input terminal for receiving a data input signal (VD), a second input terminal for receiving a scan data input signal (VSDI), a select input terminal connected to the scan enable input terminal (SE) for receiving the scan enable signal and an output terminal for outputting at least one of the data input signal (VD) and the scan data input signal (VSDI). The master latch 104 has a input terminal connected to the output terminal of the multiplexer 102 for receiving at least one of the data input signal (VDI) and the scan data input signal (VSDI), a clock input terminal connected to an output terminal of the NOT gate 106 for receiving an inverted clock signal, and an output terminal for outputting an intermediate output signal (VINT). The slave latch 108 has an input terminal connected to the output terminal of the master latch 104 for receiving the intermediate output signal (VINT), a clock input terminal for receiving the clock signal, and an output terminal for outputting an output signal (VOUT).
FIG. 1B is a timing diagram illustrating the scan-shift mode of scan testing of the scan flip-flop circuit 100. During scan testing, at time TO, the scan enable signal is at a logic high state and a first bit of the test pattern is shifted-in to the scan flip-flop circuit 100.
From T0-T1, the clock signal is at a logic low state and the multiplexer 102 outputs the first bit of the test pattern to the master latch 104. The master latch 104 receives the clock signal at a logic high state from the NOT gate 106. Thus, the master latch 104 is activated and hence, the master latch 104 outputs the intermediate output signal (VINT) at the logic state corresponding to the first bit. The slave latch 108 receives the clock signal at a logic low state and hence, is deactivated.
From T1 to T2, the clock signal is at a logic high state. The master latch 104 receives the clock signal at a logic low state from the NOT gate 106 and hence, is deactivated. However, the slave latch 108 receives the clock signal at a logic high state. Thus, the slave latch 108 is activated, and receives the intermediate output signal (VINT) and generates the output signal (VOUT) at a logic state corresponding to the first bit.
Thus, from T0 to T2, the first bit of the test pattern is shifted into the scan flip-flop circuit 100. Similarly, from T2 to T4, the second bit of the test pattern is shifted into the scan flip-flop circuit 100.
However, when the test pattern includes consecutive bits having the same logic state, i.e., when the logic state of the first and second bits of the test patterns are same, the master and slave latches 104 and 108 are clocked to shift-in the first and second bits in the scan chain. Even if the logic state of the intermediate output signal (VINT) is fixed at the logic state of the first and second bits, the clock input terminals of the master and slave latches 104 and 108 toggle based on the logic state of the clock signal. As a result, the internal components of the scan flip-flop circuit 100 (e.g., transistors and capacitors), are charged and discharged frequently, thereby leading to unnecessary power consumption. Further, due to the increase in the power consumption during scan testing, the voltage drop across the scan chain may exceed the expected voltage drop for which the scan flip-flop circuit 100 is designed, thereby reducing the voltage level of the clock signal at the clock input terminal of the scan flip-flop circuit 100 and leading to failure of the scan testing technique.
One technique to overcome the aforementioned problem is to use a clock-gating logic circuit. FIG. 2 is a schematic block diagram of a conventional integrated circuit (IC) 200 including a clock-gating circuit 202 and a flip-flop 204. The IC 200 receives a test pattern as an input signal (VIN), a clock signal and a reset signal. The clock-gating circuit 202 includes an XNOR gate 206, a NOR gate 208, and an AND gate 210.
The XNOR gate 206 has first and second input terminals for receiving an output signal (VOUT) and the input signal (VIN), respectively, and an output terminal that generates a first control signal (VCS1). The NOR gate 208 has a first input terminal connected to the output terminal of the XNOR gate 206 for receiving the first control signal (VCS1), a second input terminal for receiving the clock signal, and an output terminal for generating a second control signal (VCS2). The AND gate 210 has a first input terminal connected to the output terminal of the NOR gate 208 for receiving the second control signal (VCS2), a second input terminal for receiving the clock signal, and an output terminal for generating a clock-gated clock signal (VCGCS). The flip-flop 204 has first input terminal for receiving the input signal (VIN), a second input terminal for receiving the reset signal, and a clock input terminal connected to the output terminal of the NAND gate 210 for receiving the clock-gated clock signal (VCGCS).
In operation, when the logic states of the input signal (VIN) and the output signal (VOUT) are equal, the first control signal (VCS1) and the second control signal (VCS2) are at logic high and logic low states, respectively. The clock-gating logic circuit 202 generates the clock-gated clock signal (VCGCS) at a logic low state, thereby deactivating the flip-flop 204. However, this technique requires each flip-flop 204 of the scan chain (not shown) to have a clock-gated circuit 202, and hence, leads to a decrease in the number of flip-flops per unit area. Further, the clock-gated circuit 202 increases the propagation delay of the input signal (VIN), thereby decreasing the frequency of the clock signal. A decrease in the frequency of the clock signal increases the time required for testing the IC 200.
FIG. 3 is a block diagram of a conventional flip-flop circuit 300 used to overcome the aforementioned problem. The flip-flop circuit 300 includes a master latch 302, a clock-gating circuit 304, a slave latch 306, and a NOT gate 308. The clock-gating circuit 304 includes an OR gate 310 and a NAND gate 312.
The master latch 302 has an input terminal for receiving an input signal (VIN) that is a test pattern generated by an ATPG, a clock input terminal for receiving a clock signal, and an output terminal for outputting an intermediate output signal (VINT) based on the clock signal. The slave latch 306 has an input terminal connected to the output terminal of the master latch 302 for receiving the intermediate output signal (VINT), a clock input terminal for receiving an inverted clock-gated clock signal by way of the NOT gate 308, and an output terminal for outputting an output signal (VOUT). The OR gate 310 has a first input terminal connected to the output terminal of the master latch 302 for receiving the intermediate output signal (VINT), a second input terminal connected to the output terminal of the slave latch 306 for receiving the output signal (VOUT), and an output terminal for generating a control signal (VCS). The NAND gate 312 has first input terminal for receiving the clock signal, a second input terminal connected to the output terminal of the OR gate 310 for receiving the control signal (VCS, and an output terminal for outputting a clock-gated clock signal (VCGCS). The NOT gate 308 has an input terminal connected to the output terminal of the NAND gate 312 for receiving the clock-gated clock signal (VCGCS) and an output terminal for outputting the inverted clock-gated clock signal.
In operation, when the logic states of the intermediate output signal (VINT) and the output signal (VOUT) are low, the control signal (VCS is low. The NAND gate 312 generates the clock-gated clock signal (VCGCS) at a logic high state. The NOT gate 308 generates the inverted clock-gated clock signal (VCGCS) at a logic low state, thereby deactivating the slave latch 306. However, the master latch 302 is not deactivated. Further, when either the intermediate output signal (VINT) or the output signal (VOUT) are high, the flip-flop circuit 300 operates as a conventional flip-flop having a master-slave latch configuration. As the master and slave latches 302 and 306 are not deactivated, it results in unnecessary power dissipation. Also, the clock-gating circuit 304 increases the propagation delay of the input signal, thereby decreasing the frequency of the clock signal, which increases test time.
Therefore, it would be advantageous to have a scan flip-flop circuit that prevents charging and discharging of internal components of the scan flip-flop circuit based on the test pattern, reduces power consumption during scan testing of an integrated circuit without increasing circuit area, and does not increase test time.